The present invention relates to a semiconductor integrated circuit such as a TTL (transistor transistor logic) output circuit and, more particularly, to a TTL output circuit capable of limiting an output current when an output terminal of the TTL output circuit is short-circuited to ground potential while an output voltage thereof is at a high level.
Typically, voltage level input/output interfaces of digital integrated circuits can be generally classified into ECL (emitter coupled logic) level for high speed operation, TTL level for intermediate speed operation and CMOS level for low speed operation. However, with recent improvements in transistor performance, there is a tendency that the operation speed range to be covered by the TTL is partially overlapped with that for the CMOS level and the range to be covered by the ECL level is also partially overlapped with that for the TTL level.
A conventional TTL output circuit comprises two Darlington-connected NPN transistors. In this circuit, when the output terminal of the Darlington circuit is short-circuited to ground potential, while the output voltage thereof is high, the current flow through the Darlington circuit is large enough to cause bonding wires thereof to be melted down. Therefore, in order to limit the collector current, a resistor is connected in series with the collector of the NPN transistor at the output side of the Darlington circuit. More specifically, the potential at the above-mentioned collector is lowered by a potential drop across the resistor. This is caused by an increased collector current due to the short circuit of the output terminal, so that the transistor at the output side of the Darlington circuit is saturated, to thereby limit the output current.
This conventional output circuit processes a significant shortcoming. Specifically, the current limiting resistor, which is intended to limit the collector current, also limits a transient current of the NPN transistor at the output side of the Darlington circuit during the rise time of high speed normal operation. The speed of the normal operation is adversely affected accordingly. As the simplest way for overcoming such a drawback, removing the current limiting resistor has been proposed, that is, connecting the collector of the above-mentioned NPN transistor directly to the power source voltage. Such a measure then results in the problem of unlimited large collector current from the transistor.